RISC-V

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RISC-V (pronounced "risk-five") is a license-free, modular, extensible instruction set architecture (ISA).

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RISC-V developer room track schedule for FOSDEM 2025 (fosdem.org)

submitted 3 weeks ago by JRepin@lemmy.ml to c/riscv@lemmy.ml

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The Devroom will be held on February 1 (Saturday), 2025 in Brussels, Belgium. Topics related to RISC-V encompasses the RISC-V ISA, open source RISC-V hardware (e.g. cores, SoCs, accelerators), and open source RISC-V software (e.g. OS ports, emulators, toolchains).

The default duration for talks is 45 minutes including discussion. Presentations will be recorded and streamed.

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