RISC-V

We’re happy to share that DeepComputing’s DC-ROMA RISC-V Mainboard for Framework Laptop 13 is now in stock and shipping in the Framework Marketplace. This is very much a developer-focused board to help accelerate maturing the software ecosystem around RISC-V, so we recommend waiting for future RISC-V products if you’re looking for a consumer-ready experience. We shared more detail on the Mainboard in an earlier blog post and video, but as a quick summary, this is powered by a StarFive JH7110 processor that uses the open source RISC-V ISA. The team at DeepComputing designed it to drop directly into a Framework Laptop 13 chassis or Cooler Master Mainboard Case.

T-HEAD is a wholly owned subsidiary of Alibaba, one of China's largest tech companies. Over the past few years, T-HEAD has created a line of RISC-V cores. Alibaba seems to have two motivations for pushing RISC-V. On one hand, the company stands to benefit from creating cost effective chips optimized for areas it cares about, like IoT endpoints and edge computing. On the other, Alibaba almost certainly wants to reduce its dependence on foreign imports. RISC-V is an open instruction set, and isn't controlled by US or British corporations like x86-64 or ARM. T-HEAD's RISC-V push can thus be seen more broadly as a part of China's push to create viable domestic microchips.

Xuantie C910 slots into the "high performance" category within T-HEAD's lineup. Besides joining a small number of out-of-order RISC-V cores that have made it into hardware, C910 is an early adopter for RISC-V's vector extension. It supports RVV 0.7.1, which features masking and variable vector length support. T-HEAD has since released the C920 core, which brings RVV support up to version 1.0, but otherwise leaves C910 unchanged. From Alibaba's paper, with descriptions added in red by Clam. PIU and PLIC appear in the dual core diagram below.

C910 targets "AI, Edge servers, Industrial control, [and] ADAS" as possible applications. It's also T-HEAD's first generation out-of-order design, so taking on all those applications is ambitious. C910 is implemented in clusters of up to four cores, each with a shared L2 cache. T-HEAD targets 2 to 2.5 GHz on TSMC's 12nm FinFET process, where a C910 core occupies 0.8 mm2. Core voltage is 0.8V at 2 GHz, and 1.0V at 2.5 GHz. On TSMC's 7nm process, T-HEAD managed to push core frequency to 2.8 GHz. T-HEAD's paper further claims dynamic power is around 100 microwatts/MHz, which works out to 0.2W at 2 GHz. Of course, this figure doesn't include static power or power draw outside the core. Yet all of these characteristics together make clear C910 is a low power, low area design.

This article will examine C910 in the T-HEAD TH1520, using the LicheePi single board computer. TH1520 is fabricated on TSMC’s 12nm FinFET process, and has a quad-core C910 cluster with 1 MB of L2 running at 1.85 GHz. It’s connected to 8 GB of LPDDR4X-3733. C910 has been open-sourced, so I’ll be attempting to dig deeper into core details by reading some of the source code – but with some disclaimers. I’m a software engineer, not a hardware engineer. Also, some of the code is likely auto-generated from another undisclosed source, so reading that code has been a time consuming and painful experience. Expect some mistakes along the way.

The Devroom will be held on February 1 (Saturday), 2025 in Brussels, Belgium. Topics related to RISC-V encompasses the RISC-V ISA, open source RISC-V hardware (e.g. cores, SoCs, accelerators), and open source RISC-V software (e.g. OS ports, emulators, toolchains).

The default duration for talks is 45 minutes including discussion. Presentations will be recorded and streamed.

RISC-V has seen a flurry of activity over the past few years. Most RISC-V implementations have been small in-order cores. Western Digital’s SweRV and Nvidia’s RV-RISCV are good examples. But cores like those are meant for small microcontrollers, and the average consumer won’t care which core a company selects for a GPU or SSD’s microcontrollers. Flagship cores from AMD, Arm, Intel, and Qualcomm are more visible in our daily lives, and use large out-of-order execution engines to deliver high performance.

Out-of-order execution involves substantial complexity, which makes SiFive’s Performance P550 and T-HEAD’s Xuantie C910 interesting. Both feature out-of-order execution, though a quick look at headline specifications shows neither core can take on the best from AMD, Arm, Intel, or Qualcomm.

To check on RISC-V’s progress as its cores move toward higher performance targets, I’m comparing with Arm’s Cortex A73 and Intel’s Goldmont Plus. Both have comparably sized out-of-order execution engines.

Geekbench 6.4 introduces support for RISC-V Vector Extensions, boosting the performance of workloads that leverage SIMD instructions when run on RISC-V CPUs that implement RVV.

RISC-V is a relatively young and open source instruction set. So far, it has gained traction in microcontrollers and academic applications. For example, Nvidia replaced the Falcon microcontrollers found in their GPUs with RISC-V based ones. Numerous university projects have used RISC-V as well, like Berkeley’s BOOM. However, moving RISC-V into more consumer-visible, higher performance applications will be an arduous process. SiFive plays a key role in pushing RISC-V CPUs toward higher performance targets, and occupies a position analogous to that of Arm (the company). Arm and SiFive both design and license out IP blocks. The task of creating a complete chip is left to implementers.

By designing CPU blocks, both SiFive and Arm can lower the cost of entry to building higher performance designs in their respective ISA ecosystems. To make that happen within the RISC-V ecosystem though, SiFive needs to develop strong CPU cores. Here, I’ll take a look at SiFive’s P550. This core aims for “30% higher performance in less than half the area of a comparable Arm Cortex A75.”

Just as with Arm’s cores, P550’s performance will depend heavily on how it’s implemented. For this article, I’m testing the P550 as implemented in the Eswin EC7700X SoC. This SoC has a 1.4 GHz, quad core P550 cluster with 4 MB of shared cache. The EIC7700X is manufactured on TSMC’s 12nm FFC process. The SiFive Premier P550 Dev Board that hosts the SoC has 16 GB of LPDDR5-6400 memory. For context, I’ve gathered some comparison data from the Qualcomm Snapdragon 670 in a Pixel 3a. The Snapdragon 670 has a dual core Arm Cortex A75 cluster running at 2 GHz.

direct Youtube link: https://youtube.com/watch?v=4TmHSsIU1ns

cross-posted from: https://lemmy.world/post/24756689

Hello all,

I've only done very basic research on RISC-V as the DeepCompute RISC-V mobo caught my attention. For the software side, I know that support will (probably) come with time, so I can't really do much besides lament over it huh?

The main thing that caught my eye is that the DeepCompute mobo seems to only accept SD cards for storage. Is this a hard limit of RISC-V or is it just a limit of current technology (i.e. we need time to build something over RISC-V like x86_64/amd64?)?

I've also heard that Linux ran vaguely slow on RISC-V architectures, but ive only heard it as a passing comment. How true is this? Would future developments/putting in more time like for the decades behind x86_64 developments alleviate the speed issue?

Thank you all!

Finally my 6€ come back 😓 Source: https://x.com/milkv_official/status/1879799138705195303

You might get intimidated when you hear OS or kernel development, the basic functions of an OS (especially the kernel) are surprisingly simple. Even Linux, which is often cited as a huge open-source software, was only 8,413 lines in version 0.01. Today's Linux kernel is overwhelmingly large, but it started with a tiny codebase, just like your hobby project.

We'll implement basic context switching, paging, user mode, a command-line shell, a disk device driver, and file read/write operations in C. Sounds like a lot, however, it's only 1,000 lines of code!

[…]

In this book, I chose RISC-V as the target CPU because:

• The specification is simple and suitable for beginners.
• It's a trending ISA (Instruction Set Architecture) in recent years, along with x86 and Arm.
• The design decisions are well-documented throughout the spec and they are fun to read.

We will write an OS for 32-bit RISC-V. Of course you can write for 64-bit RISC-V with only a few changes. However, the wider bit width makes it slightly more complex, and the longer addresses can be tedious to read.

A team from China’s top government research academy pledged to produce this year a processor based on the open-source chip-design architecture RISC-V, as Beijing advances its semiconductor self-reliance drive amid escalating US restrictions.

The Chinese Academy of Sciences (CAS) will be able to deliver its XiangShan open-source central processing unit in 2025, wrote Bao Yungang, deputy director at the academy’s Institute of Computing Technology, in a Weibo post on Sunday.

cross-posted from: https://lemmy.bestiver.se/post/174306

Comments

cross-posted from: https://lemmy.world/post/23802973

Can it topple x86 and Arm, or is the gap too wide to close?

Finally! After weeks of work, I have successfully booted postmarketOS on both of those devices. This should hopefully make the adoption of both, RISC-V and PostmarketOS easier.

The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.

The RISC-V architecture defines four basic modes (32-bit, 32-bit for embedded systems, 64-bit, 128-bit) and several extensions. For instance, the support for single precision floating-point numbers is added by the F extension.

The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations. The RVV instructions can be split into three groups:

• related to masks,
• integer operations,
• and floating-point operations.

When a CPU does not support floating-point instructions, it still may provide the integer subset.

RVV introduces 32 vector registers v0, ..., v31, a concept of mask (similar to AVX-512), and nine control registers.

Unlike other SIMD ISAs, RVV does not explicitly define size of vector register. It is an implementation parameter (called VLEN): the size has to be a power of two, but not greater than 216 bits. Likewise, the maximum vector element size is an implementation parameter (called ELEN, also a power of two and not less than 8 bits). For example, a 32-bit CPU might not support vectors of 64-bit values.

But generally, we may expect that a decent 64-bit CPU would support elements having 8, 16, 32 or 64-bit, interpreted as integers or floats.